1. Technical Field
Various embodiments generally relate to a semiconductor apparatus, and more particularly to a clock generation circuit capable of generating a clock signal and a semiconductor apparatus having the same.
2. Related Art
A semiconductor system may include a plurality of semiconductor apparatuses. When an interface circuit for data communication exchanges data between the semiconductor apparatuses, a clock signal may be used to synchronize data communications.
To increase operation speed, a sub-rate multi-phase clock signal may be used instead of a full-rate clock signal, and a phase locked loop (PLL) or a delay locked loop (DLL) may be used to generate a multi-phase clock signal having a predetermined phase difference from a system clock signal or a reference clock signal. However, due to the complexity of circuit, the phase locked loop and the delay locked loop may occupy a large space. In addition, they may consume a large amount of power and need a locking time.